1. Field of the Invention
The present invention relates to circuitry for generation of periodic signals such as clock signals. More specifically, the present invention relates to digital delay locked loop circuits (DDLLs) having improved stability and performance.
2. Discussion of Related Art
Many high speed electronic systems possess critical timing requirements which dictate the need to generate a periodic clock wave form that possesses a precise time relationship with respect to some reference signal. The improved performance of computing integrated circuits (ICs) and the growing trend to include several computing devices on the same board present a challenge with respect to synchronizing the time frames of all the components.
While the operation of all components in the system should be highly synchronized, i.e., the maximum skew or difference in time between the significant edges of the internally generated clocks of all the components should be minute, it is not enough to feed the reference clock of the system to all the components. This is because different chips may have different manufacturing parameter which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks.
Conventionally, synchronization is achieved by using DDLL circuits to detect the phase difference between clock signals of the same frequency and produce a digital signal related to the phase difference. By feeding back the phase difference-related signal to control a delay line, the timing of one clock signal is advanced or delayed until its rising edge is coincident with the rising edge of a second clock signal.
The operation of conventional DDLLs is shown in FIGS. 1 and 2. In FIG. 1, clock input buffer 104, delay lines 101, 102, and data output buffer 109 constitute an internal clock path. Delay line 101 is a variable delay generator with a logic-gate chain. A second delay line 102 is connected to replica circuits 108, which emulate the internal clock path components. Replica circuits 108 include dummy output buffer 110, with dummy load capacitance 111 and dummy clock buffer 107. The dummy components and second delay line 102 constitute a dummy clock path having exactly the same delay time as the internal clock path. Shift register 103 is used for activating a number of delay elements in both delay lines based on a command generated by phase comparator 106.
Phase comparator 106 compares the dummy clock and the external clock phases which differ by one cycle. This comparison is illustrated in FIGS. 2A, 2B, 2C, and 2D. External clock signal 200 is divided down in divider 105 to produce divided-down external signal 201. Signal 202 is the signal at the output of dummy delay line 102. Signal 203, which is generated inside phase comparator 106, is a one delay unit delayed output dummy line signal 202. If both signals 202 and 203 go high before 201 goes low, this means that the output clock is too fast and phase comparator 106 outputs a shift left (SL) command to shift register 103, as illustrated in FIG. 2B. Shift register 103 shifts the tap point of delay lines 102 and 101 by one step to the left, increasing the delay. Conversely, if both signals 202 and 203 go high after 201 goes low, this means that the output clock is too slow and phase comparator 106 outputs a shift right (SR) command to shift register 103, as illustrated in FIG. 2D. Shift register 103 shifts the tap point of delay lines 102 and 101 by one step to the right, decreasing the delay. If 201 goes low between the time 202 and 203 go high, the internal cycle time is properly adjusted and no shift command is generated, as illustrated in FIG. 2C. The output of the internal clock path in this case coincides with the rising edge of the external clock and is independent of external factors such as ambient temperature and processing parameters.
Conventional DDLLs, however, suffer from numerous drawbacks. One such drawback occurs in the event the DDLL is placed in a state of minimum or maximum delay. A state of minimum delay occurs when the delay between the input and output clock signals is as close to zero as allowed by the parameters of the delay line (i.e. when the tap point is at the very end of the delay line). In this case, if the DDLL attempts to decrease the delay, such decrease would be impossible because the delay line is already at minimum delay. Conversely, maximum delay occurs when the DDLL is as close to maximum delay as allowed by the parameters of the delay line (i.e. when the tap point is at the opposite end of the delay line). In the latter case, if the DDLL attempts to increase the delay, such increase would be impossible because the delay line is already at maximum delay. In these minimum and maximum delay states, the DDLL would be inoperable. A solution to this problem may be achieved by constructing a wrap-around loop, so that when the DDLL is at minimum delay, the delay line would shift around to maximum delay. This is not an optimal solution, however, because delay lines are typically of significant length and a lock could be achieved with a harmonic of the signal, which is undesirable.
Another drawback of conventional DDLLs is that they are inherently inaccurate. This inaccuracy is due to the fact that they compare a divided down version of the input clock signal, rather than the actual input clock signal, with the output clock signal, as shown in FIG. 2.
A further drawback of conventional DDLLs is that they are inherently inaccurate due to asymmetries in the delay line design. Typical logic-gate delay elements in conventional DDLLs are shown in FIG. 8 and operate as follows. Delay line 52 includes series connected delay elements, each delay element 51 consisting of two NAND gates and an inverter. The external clock is input into delay line 52 through a selected tap point, indicated by a high logic state in shift register 50. Depending on the command generated by the phase comparator (SL, SR, or no change), shift register 50 moves the tap point one delay element to the left or right, or does not shift the tap point. Unless the pull-up and pull-down times of the transistors forming the inverters and NANDs in each delay element are identical, however, the output of delay line 52 will consist of pulses with asymmetrical rising and falling edges. This asymmetry leads to differing time periods between any two rising and falling edges, as shown in FIG. 9(a). The output signal, therefore, will differ in shape from the input signal, which may lead to inaccuracies.
Yet another drawback of conventional DDLLs is that they operate under the constraint of random-initialized logic starting up at unknown values. This problem is typically resolved in conventional DDLLs by using initialization circuitry to power up the DDLL at some predetermined value. A drawback of this method of resolving the random-initialized logic problem is that if the initialization circuitry fails, it will be impossible for the DDLL to operate.
There is a need, therefore, to improve the performance of DDLLs by resolving the inoperability of the DDLL in states of minimum and maximum delay without losing accuracy due to the possibility of locking on to a harmonic of the signal, rather than the actual signal. Further, there is a need for increasing the accuracy of DDLLs by achieving a lock with the actual input signal, rather than a divided-down version of the input signal. Additionally, there is a need for improving the performance of DDLLs by providing a symmetrical delay line output signal. Finally, there is a need for improving the accuracy and performance of DDLLs by ensuring insensitivity to random-initialized logic at power up.